Implementation and Characterization of 14 nm Trigate HOI n-FinFET using Strained Silicon channel with reduced area on chip

With the tremendous scaling of planar MOSFETs to keep abreast with Moore's law, the performance of the MOSFET devices have degraded due to the Short Channel Effects. This led to the design of multiple gate FETs like double gate FinFETs and Trigate FinFETs beyond 90 nm technology. However, beyond 32 nm technology, even FinFETs are not immune to short channel effects. So another way to increase the drain current is the use of strain technology. In this paper, a 3D 14 nm gate length Trigate FinFET with a tri-layered strained silicon channel comprising of two silicon layers and a Si
_0.8
Ge
_0.2
layer sandwiched in between is developed and its electrical characteristics are compared to another 14 nm gate length Trigate FinFET having only silicon channel. The electrical parameters of both the devices with a reduced chip area are analyzed and compared, such as I
_on
/I
_off
current ratio, threshold voltage, subthreshold slope and DIBL. The results show improved performance of the developed device by using strained channel while consuming reduced chip area.