Ferroelectric Hafnium Zirconium Oxide Compatible With Back-End-of-Line Process

To scale the ferroelectric random access memory (FeRAM) technology toward 28 nm or beyond, it is critical to develop stacked capacitor (with sufficient surface area) to allow good sense margin for the 1-transistor- 1-capacitor (1T1C) bit cell. Therefore, to enable 3-D integration in back-end-of-line (BEOL) process, it is essential to optimize the fabrication recipes in low-thermal budget (<; 400 °C). In this regard, we investigated the low-temperature process for ferroelectric Hf
_0.5
Zr
_0.5
O
₂
(HZO) capacitor with the plasma-enhanced atomic layer deposition (PEALD). It was found that, with sufficient annealing time (>50 s) in low temperature (\sim 350 °C), the ferroelectric properties of HZO could be fully manifested. No degradation is shown in the remnant polarization ( P
_r
) under the optimized low-temperature process. Furthermore, the retention/endurance characteristics with different P
_r
states were measured to determine the minimally required write voltage. Finally, the SPICE simulation is conducted to evaluate the sense margin of the projected 28-nm 1T1C array with stacked cylindrical capacitors using the measured P
_r
drift behavior over time.