3–9-GHz CMOS LNA Using Body Floating and Self-Bias Technique for Sub-6-GHz 5G Communications

We propose the body floating and self-bias technique, in which the body of the transistor is connected to its drain through a resistance (13.6 kΩ in this work). A low-power 3-9-GHz CMOS low-noise amplifier (LNA) using the technique for sub-6-GHz 5G systems is reported. An enhancement in S
₂₁
and noise figure (NF) of the LNA is achieved due to the forward body-to-source bias ( V
_BS
) (i.e., small threshold voltage V
_th
) and the transistors being free from the substrate leakage. Low power is achieved since low supply voltage ( V
_DD
) of 1 or 0.8 V is applicable because of small V
_th
. At V
_DD
of 1 V, the LNA consumes 3.3 mW and achieves prominent S
₁₁
of - 10.1 to -41.6 dB, S
₂₁
of 10.7 dB, and NF of 2.89 dB for 3-9 GHz. At V
_DD
of 0.8 V, the LNA consumes 1.36 mW and achieves S
₁₁
of - 10 to -45.8 dB, S
₂₁
of 9.4 dB, and NF of 3.46 dB. To the authors' knowledge, both are one of the lowest power values ever reported for CMOS LNAs with bandwidth greater than 6 GHz and NF under 3.5 dB.