A Low Jitter Digital Loop CDR Based 8–16 Gbps SerDes in 65 nm CMOS Technology

This paper presents a digital loop-based CDR endorsed in a SerDes system which can operate up to 16 Gbps. The proposed CDR employs a dynamic loop-gain control to achieve high jitter tolerance along with low power dissipation. Implemented in CMOS 65 nm technology, the proposed CDR recovers the sampling clock with an rms jitter of 850 fs and achieves a jitter tolerance of 0.5 UIpp at 7.17 MHz. The architecture can also correct the frequency offsets of up to 100 ppm between the input data rate and clock frequency. The CDR system consumes 30 mW from a 1.2 V supply, achieving an FoM of 1.9 pJ/bit.