P-FMA: A Novel Parameterized Posit Fused Multiply-Accumulate Arithmetic Processor

IEEE 754-2008 based Floating Point Unit (FPU) is computationally complex and consumes higher resources depending on precision and dynamic range viz. half/ single/double/quad precision. In order to optimize and balance the resources with Accuracy Vs Precision Vs Dynamic range, researchers had recommended and adopted trans-precision arithmetic or approximate arithmetic. Posit data type is an alternate to IEEE 754 floats providing an increased precision and dynamic range for the same data size. Fused functional units are the perfect fit for optimizing resources for arithmetic computations. This work presents algorithm and microarchitecture design of a novel parameterized and 5 stages pipelined Posit fused multiply and accumulate (P-FMA) unit which performs addition, subtraction, multiplication and multiply and accumulate operations. Our unit has been verified with random test vectors and IEEE float to Posit converted test-vectors generated from FPGen and Berkeley Test Float with Soft Posit's output as reference. Code coverage analysis of P-FMA showed that IEEE floats to posit converted vectors yielded higher coverage and better verification. The unit has been synthesized on FPGA and the results have been compared with other contemporary Posit FMAs. Our work has lesser critical path and comparable area. Our FMA unit was integrated with Posit divide and square root unit for verification with a kernel and validated with evaluation of Pi (n) adopting Chudnovsky algorithm to investigate the accuracy of our Posit FMA. The Pi estimates from Posit (64, es=lto 6) have been compared with an IEEE 754 FPU (double precision) based Pi estimate. Our P-FMA integrated with other Posit units could enable computing Pi to 16 digit accuracy in reference to Y-Cruncher, as compared to 15 digits accuracy of IEEE Double-Precision float.