Automated Low-Cost SBST Optimization Techniques for Processor Testing

Non-intrusive Software-based Self-testing (SBST) approaches are widely used for at-speed testing of complex processors. But it would be difficult for the tester to apply larger SBST programs with longer execution time on the processor. So, following the test synthesis, test codes are subjected to an automated optimization phase with the help of enhanced assembly code compaction techniques. However, comprehensive, instruction-by-instruction test compaction techniques could be computationally intensive. So, towards achieving better tradeoff between the test compaction and computational effort required for the test compaction, a two-stage compression technique is introduced in this work. In the first stage, the test program is preprocessed using a novel data dependence graph-based reduction technique. The remaining set of instructions are compressed in the second stage using a top to bottom instruction restoration technique. This stage of optimization delivers good compaction rate with the help of low-cost, high-level logical simulations. In these stages, we exploit the randomized nature of instructions of SBST test programs that were developed using automated evolutionary approaches. Finally, an adequate compaction is observed for the input test program using our method which consumed lesser number of fault simulations, allowing a low-cost test compaction.