A 27S/32S DC-balanced line coding scheme for PAM-4 signaling

We propose a simple and completely DC-balanced line coding scheme with an easily implementable encoder and decoder for 4-level Pulse Amplitude Modulation (PAM-4) signaling. This scheme provides a simple solution for implementing encoder/decoder using combinational logic with very less amount of memory usage, as compared to memory inefficient index-mapped encoder/decoder schemes. The proposed scheme ensures that every encoded word is DC-balanced and makes it highly useful for AC coupled wire-line communication links, which suffer from baseline wander that leads to erroneous detection. The proposed 27S/32S scheme has an overhead of 18.52% with a reduced maximum run length. Apart from improving Bit Error Rate (BER) by eliminating baseline wander, it also ensures zero-crossing transitions in each encoded word, enabling easy recovery of the clock at the receiver.