A 0.4µA Offset, 6ns Sensing-time Multi-level Sense Amplifier for Resistive Non-Volatile Memories in 65nm LSTP Technology

Physical limitations in scaling of Non-Volatile Memories (NVMs) necessitates alternative ways to increase on-chip storage density and reduce cost. New technologies like MRAMs and PCM, offer advantages in terms of speed and can enable replacement of embedded volatile RAMs with NVMs. Further, storing multiple bits in NVM enables reduction in cost-per-bit. In this work, we propose a four-level sense amplifier (SA) targeted for use in multi-bit resistive NVMs. The proposed, parallel-sensing, multi-level SA has better offset tolerance, double sensing margin, strong positive feedback, and high read stability. Implementation in 65nm LSTP technology achieves 25% faster sensing time (tSEN) than state-of-the-art parallel-sensing design while consuming 28% lesser power at a nominal supply voltage (VDD) of 1.0 V. The proposed design is also 20% denser than the state-of-the-art serial-sensing scheme.