Memory Performance Optimization

Summary form only given, as follows. The complete presentation was not made available for publication as part of the conference proceedings. Many of the implementation technology scaling trends the computing industry has historically relied on have started to taper off or are posing increasing design challenges. This has led to the proliferation of many-core processors and accelerators, advanced packaging technologies, and innovations in memory architecture which, in aggregate, are enabling increasingly sophisticated node organizations. However, these nodes also consist of complex memory organizations that necessitate careful data management to achieve high hardware utilization. The need for such data management is making memory performanceoptimization particularly important. This talk will illustrate examples in memory access monitoring and memory-aware data structures that show the significant performance potential that can be realized by treating memory as a first-class citizen. Further, motivated by these specific point examples, the talk will also highlight general areas for further hardware-software collaborative research and innovation aimed at further improving memory performance in future computing systems.