A 0.3-V Conductance-Based Silicon Neuron in 0.18 μm CMOS Process

This brief presents a conductance-based neuron that is capable of operating under ultra-low-voltage supplies. The proposed neuron employs a variable-gain low-pass filter to linearly integrate the input spikes onto the membrane capacitance. A positive feedback topology is used to generate output spikes and implement a frequency adaption mechanism. A differential amplifier is as well employed as a comparator to reset the membrane potential and set a threshold voltage to control the spike generator circuit. The mathematical analyses result in a first-order linear equation for membrane current of the neuron. The designed neuron was fabricated in TSMC 0.18
$\mu \text{m}$
CMOS technology with an area of 993
$\mu \text{m}^{2}$
that consumes 135 fJ/spike under a 0.3-V supply voltage. The experimental results show frequency adaption mechanism and intrinsic chattering, while regular and fast-firing behaviors are achieved by adjusting control parameters.