Soft-Error Susceptibility in Flip-Flop in EUV 7 nm Bulk-FinFET Technology

This paper presents single-event upset (SEU) rates in flip-flops (FFs) in EUV 7 nm bulk-FinFET technology. EUV technology achieves high transistor-density, small FF cell-size, and low SEU rate. The alpha-SEU rate in EUV 7 nm FFs is 0.7X of the SEU rates in 10 nm FFs. The neutron-SEU rate in EUV 7 nm FFs is 0.6X of the SEU rates in 10 nm FFs. This paper also discusses the circuit dependence of the SEU rate in Normal-, Reset-, Set-FFs, and a soft-error immune FF (SEIFF), and SRAM.