Hardware-Efficient ASIC Implementation of Eigenvalue Based Spectrum Sensor Reconfigurable-Architecture for Cooperative Cognitive-Radio Network

Spectrum sensing is an imperative process that primarily affects the reliability of cognitive radio networks (CRNs). Cooperative spectrum sensing (CSS) is the contemporary process of detecting the occupancy of spectrum by licensed users in CRN. It outperforms the conventional stand-alone spectrum-sensing (SSS) algorithms. However, such CSS algorithms have higher implementation-complexity than SSS algorithms, resulting in higher resource utilization and alleviating the hardware efficiency. Our work focuses on the design of hardware efficient VLSI-architecture for such CSS algorithms. Specifically, this paper proposes reconfigurable VLSI-architecture of cooperative spectrum sensor (CSR) for both maximum-minimum eigenvalue (MME) and maximum eigenvalue (MED) based CSS algorithms for the data-fusion based CRN. This CSR architecture has been designed based on iterative and shift power-methods to compute maximum and minimum eigenvalues in MME and MED CSS-algorithms. The proposed reconfigurable-CSR is fabricated in UMC 130-nm CMOS process and it has a die dimension of h × w =3D 1.5 mm × 1.5 mm. Furthermore, this work presents the analysis of hardware-complexity, sensing-time and performance with the increasing number of secondary users (or antenna array of CSR) in CRN. Eventually, the fabricated ASIC chip of CSR has been tested and verified in a real-world test environment.