Self-Timed Write Aid Circuit for Tall Memories in Advanced CMOS Technologies

As CMOS technology scales with complex lithography, metal resistance increases. Specifically, at high-temperatures IR drop limits the performance and impacts the yield of CMOS circuits. For SRAM, bitline resistance limits the writeability of bitcells. This paper proposes a self-timed Write Aid circuit that helps the write driver by discharging the bitline from its opposite side. The use of this aid circuit at performance worst corner, improves write time by more than 40%. For a fixed wordline pulse width of 250ps, there is around 1.5 sigma write yield improvement at 0.765v operation. The proposed circuit has been implemented and Si validated in 7nm technology.