A Low EMI Transmitter for DRAM Interface with Quadrature Clock Corrector

This paper presents a transmitter with quadrature clock corrector (QCC) and phase controller for reducing EMI problem. The phase controller consists of phase interpolator and transmission gate (TG). The transmission gate is added to turn function on and off. The quadrature clock corrector is used for signal integrity. The circuit is designed in 180-nm CMOS process using 1.8-V supply. The operating frequency is 3.2 Gbps. For duty cycle distortion of 30% ~ 70% and phase error of ±30 degrees, the maximum duty cycle error of corrected clock is about 0.4%, and the phase error between the OUT0 and OUT90 signal is up to about 3.9 degrees. The duty correction time is about 5ns and phase correction time is about 36ns. And the maximum current peak of output drivers is 23% less than that of conventional transmitter.