A Discrete-Time Delta-Sigma Modulator with Relaxed Driving Requirements And Improved Anti-Aliasing

This paper presents a switched-capacitor integrator for discrete-time delta-sigma modulators. Compared to the conventional implementations, the proposed switched-capacitor integrator reduces the power consumed by the input buffer that drives the delta-sigma modulator, by a factor of two. The proposed integrator samples the input in two non-overlapping phases instead of sampling it in a single phase. This way, the input capacitance can be equally distributed among the two phases, resulting in a 2× reduction in the switched capacitor load that needs to be driven by the input buffer. We further show that doing this also introduces notches in the signal-transfer- function of the modulator at odd-multiples of the sampling frequency, thereby preventing aliasing from those frequencies. The proposed integrator is used to design a fourth-order DTDSM in a 180 nm CMOS process. Simulation results show that the modulator achieves a peak signal-to-noise ratio (SNR) of 97.9 dB while consuming 0.86 mW of power.