A Phase Domain Excess Loop Delay Compensation Technique with Latency Optimized Phase Selector for VCO-Based Continuous-Time ΔΣ ADC

This paper presents a phase domain excess loop delay compensation (ELDC) technique for voltage-controlled oscillator-based (VCO-based) continuous time (CT) ΔΣ ADC. The ELDC is achieved by shifting the phase of the sampling clock which composes a zero-order feedback loop in phase domain and avoid long latency between quantizer and DAC. The phase shifting is realized by a phase selector which selects the sampling clock from multi-phase clock signals generated by the phase interpolator. To ensure the stability of the ΔΣ ADC, a two-step phase selector is proposed to optimize the latency in the zero-order feedback loop. Simulation results shows that the proposed technique can effectively compensate ELD in phase domain and low latency feature in the feedback loop makes the technique suitable for high speed VCO-based CT ΔΣ ADC.