SAM: A Segmentation Based Approximate Multiplier for Error Tolerant Applications

In recent times, approximate computing has found significant use in applications that can tolerate partially inaccurate results. This tolerance can be exploited to design simpler hardware aimed at getting area and energy benefits. In this work, we propose a novel technique to multiply two unsigned binary numbers through a Segmentation based Approximate Multiplier (SAM). The proposed design reduces the size of the Partial Products Matrix (PPM) in the order of n × (2n — 1) to a Reduced Partial Product Matrix (R-PPM) of the order 4 × 2n. Additionally, it also eliminates the extra hardware required for compression and rearrangement of partial products. μ-SAM, an optimized version of our basic design is also proposed along with this work. μ-SAM further minimizes the on-chip area and power consumption of the basic design. The basic design consumes 32.43% lesser on-chip area when compared to the conventional Wallace tree multiplier [1] and produces results that are 89.1% more accurate when compared to other existing state-of-the-art designs such as TOSAM [2], LETAM [3], and DQ4:2C4 [4].