A 12-Bit 100MS/s SAR ADC with Digital Error Correction and High-Speed LMS-Based Background Calibration

ADC is a significant block in wireless systems, which requires high bandwidth of hundreds of MHz and high resolution of 12-bits. Successive-approximation register (SAR) ADC is an energy efficient architecture but its conversion speed is generally restricted. This paper proposed a scheme to enhance the speed and lower the power consumption of the Least Mean Square (LMS) background calibration, so that it can be used in the design of high-speed SAR ADC. The DEC technique is designed based on the non-binary search, which tackles the insufficient DAC settling, so the conversion speed can be enhanced. Furthermore, the LMS-based background calibration can also improve the linearity of the ADC, so the accuracy of the SAR ADC increases. The proposed SAR ADC is designed in a standard 55 nm CMOS technology with a core area of 0.08 mm2. It consumes 3.59 mW at 100 MS/s sampling rate, achieving a SNDR of 66.78 dB. A good figure of merit (FoM) of 20.13 fJ/conversion-step is obtained.