ICML: Machine Learning-based Transistor-level Integrated Circuit Layout Error Classification using Color Analysis and Segmentation

Integrated circuit (IC) layout designs must conform to formalized and non-formalized constraints. These constraints are often embedded in physical design software in the form of design rule checking. IC layout designs are verified through the help of design rule checking (DRC), layout vs. schematic (LVS), and manual inspection courtesy of the design engineer. However, manually inspecting every layout design for errors is slow and impractical. This problem has led to the proposal of utilizing a combination of machine learning, deep learning, and computer vision methods to verify the integrity of IC layout designs. The goal of this study is to present a methodology to automatically detect and classify IC transistor layout errors. A color-based feature characterization technique was used to extract the features from IC layout images. In addition, machine learning models for multioutput-multiclass classification were explored to classify errors on IC layouts. Classification metrics such as macro average, precision, recall, and F1-score were used to evaluate the performance of the proposed system. As a result, random forest obtained 99.75% on classifying error types while multilayer perceptron obtained 92.26% on classifying error sub-categories of transistor-level integrated circuit layouts.