Comprehensive modeling and evaluation of Network-on-Chip performability

The rapidly increasing transistor density enables the evolution of many-core on-chip systems. Networks-on-Chips (NoCs) are the preferred communication infrastructure for such systems. Besides, NoCs have also been proposed to solve the complex on-chip communication in the three-dimensional systems-on-chips (3D SoCs). A downside of technology scaling is the increased susceptibility to failures in NoC resources. It is challenging to analyze the performance and reliability of degradable NoCs. In this paper, we propose a generic framework to evaluate the performability of both 2D and 3D NoCs under consideration of different fault models. Moreover, we use a partially-connected 3D Mesh and hexagonal NoCs to demonstrate our framework. Transient performabilities of the 3D fault-tolerant negative-first (3D-FTNF) and elevator-first routing algorithms are evaluated. Finally, we compare the transient performabilities of a hexagonal NoC and a mesh NoC.