Fast Polygons Proximity Detection for ICs Multiple Patterning Lithography

Multiple Patterning Lithography (MPL) is one of the main solutions to manufacture ICs with scale less than 32 nm using 193nm optical lithography. This approach is based on layout decomposition according to the topology of IC layout geometries. The main difficulty for its application is the huge amount of calculations aimed to determine proximity of IC layout polygons. In this article a new approach to minimize the amount of calculations during proximity evaluation is proposed. It is based on implementation of special data structure for storing the geometries of an IC with the sparse matrices storage format used to minimize the memory usage. Experimental results show that proposed approach gives an advantage in terms of memory usage and evaluation speed. Funding: the reported study was funded by RFBR, project number 20-07-00556.