Equality NoC: A Novel NoC Topology for High Performance and Energy Efficiency

Manycore processors on a single chip have been a trend in recent years because the breakthrough of lithography semiconductor manufacturing process to 7 nm-node and beyond make higher efficient CPUs and FPGAs. The interconnect network is the key of the performance while hundreds to thousands of cores are connected. Mesh and torus topologies are often used but they become lower efficient in many cores in the processor. We propose a novel on-chip network named Equality NoC. They are from the Equality topology. We use ten links to build a low-radix network topology to compare with 5D torus topology. The system is a 32,768-core model and the simulations were performed by BookSim 2.0 package. The model is three-time larger than the art-of-date manufacturing technology of GPU by 10,790 cores. Except similar performance under asymmetric traffic, and higher throughput by 5D torus under bitcomp traffic, Equality NoC performs better under eight traffics including uniform and transpose traffics. Equality NoC perform with lower latency in nine traffics except asymmetric by zero-load latency. For this research, we propose Equality NoC as a novel on-chip network topology with better scalability, flexibility, and energy-saving than 5D torus topology.