High Speed Data Transactions for Memory Controller Based on AXI4 Interface Protocol SoC

Recently, the latency resulted from the communication between the multi-core processor IP cores and the other IP cores such memory controller and peripherals on the same die SoC became a critical issue especially when all the core processors using advanced interface protocol such AXI4 and make write and read transactions in different burst mode capability. In this paper, we proposed a multi-core memory controller for four core processors using the AXI4 interface protocol. The multi-core memory controller can make the write and read transactions using the AXI4 interface protocol in parallel to improve the entire system speed up on the same die SoC. The SoC design architecture is modeled in System Verilog HDL, simulation and synthesis are done by using the Vivado tool and FPGA ZYNQ-7 ZC702 Evaluation Board (xc7z020clg484-1).