Differential Edge-Modulated Signaling With Encoded Clock and Dynamic Data Rate Scaling

This letter describes a differential edge modulation signaling scheme for a wireline link where the edge position is differentially modulated on a pair of wires such that data bits are recovered when these signals sample each other. Therefore, this clock-encoded modulation scheme eliminates the need for receiver side clock generation and timing recovery and enables matched source-synchronous jitter tracking with >500-MHz bandwidth. An agile multiplying injection-locked oscillator drives the link and dynamically scales the data rate from 3 to 10 Gb/s with less than 10-ns response time. Using a decision-based time-domain equalizer, the link can compensate the 20-dB loss at 10-Gb/s consuming only 19.4 mW, and scales to 10 mW at 3 Gb/s without supply scaling.