Massively parallel inner-product array processor

We present a hardware architecture for parallel inner-product array computation in very high dimensional feature spaces, towards a general-purpose kernel-based classifier and function approximator. The architecture is internally analog with fully digital interface. On-chip analog fine-grain parallel processing yields real-time throughput levels for high-dimensional classification tasks. The architecture contains an array of computational cells with integrated digital storage and a parallel bank of A/D converters. Digital multiplication with enhanced resolution is obtained with bit-serial input vectors and bit-parallel storage of weights, by combining quantized outputs from multiple rows of binary unit cells over time. A prototype 128/spl times/512 inner-product array processor on a single 3 mm /spl times/3 mm chip fabricated in standard CMOS 0.5 /spl mu/m technology achieves 8-bit effective resolution. An efficient real-time massively-parallel hardware architecture of a support vector machine classifier is presented.