Single-Phase Transfer Delay FLL With Enhanced Performance for Power System Applications

This article proposes a gradient descent-based transfer delay frequency-locked loop (FLL) (GDTD FLL) to effectively address the challenges of existing transfer delay-based FLLs in terms of unacceptable frequency and phase angle overshoots during variations in the supply voltage amplitude and distorted voltage conditions. In the proposed GDTD FLL, a linear model of the distorted single-phase supply voltage is developed and the error term is constructed. Consequently, the gradient descent algorithm is employed to drive the error term to zero and provide an estimate of the FLL expression from which frequency estimation is achieved. By designing the learning rate employed in the gradient descent algorithm, a degree of freedom is introduced in the proposed GDTD FLL, giving it the ability to achieve improved performance during variations in the supply voltage amplitude. Furthermore, a delay-based harmonic cancellation approach is developed to reject supply voltage harmonics in the FLL’s phase angle estimation. The effectiveness of the proposed GDTD FLL is verified in comparison with other single-phase FLL schemes through experimental studies where it is shown that the proposed GDTD FLL effectively addresses the challenges of existing delay-based FLLs in terms of peak frequency and phase angle overshoots, especially when the supply voltage undergoes amplitude variation or distortion.