Motion estimation operation implemented in FPGA chips for real-time image compression

Motion estimation is a very computational demanding operation during the video compression process, thus special hardware architectures are required to achieve real-time compression performance. Advantages in increasing complexity, density and speed of programmable logic devices will soon allow us to implement this kind of application specific processor within one programmable chip. This paper evaluates the performance of block matching hardware architectures implemented in Xilinx FPGA. Systolic arrays for a full search algorithm inferred by T. Komarek and P. Pirsch (1989) have been implemented and evaluated in terms of the achieved clock rate and number of occupied FPGA resources. Results show that, with 2D type systolic arrays, it is possible to achieve real-time performance of motion estimation for CIF images even with a moderate capacity (250 k gates) FPGA chip.