An Adaptive Method for DC Current Reduction in Totem Pole Power Factor Correction Converters

Enabled by improved wideband gap semiconductor devices, the bridgeless totem pole power factor correction (PFC) converter is becoming an increasingly popular topology for front end ac input of high power battery chargers and telecom power supplies, achieving high efficiency as well as low electromagnetic interference. Unlike the conventional boost PFC, in a totem pole structure, different circuits are used for shaping the current in positive and negative half cycles. As a result, sensing inconsistencies may result in a significant dc component in the input current. In field applications, accumulation of dc currents from multiple PFC rectifier based loads can potentially lead to saturation of distribution transformers. This article proposes a low-cost method for adaptive detection and reduction of the dc input current based on time domain analysis of the dc link voltage. The effectiveness of the method in compensating manufacturing tolerances is experimentally validated on a 390 V, 1450 W interleaved totem pole PFC converter, and dc current reduction of up to 99.6% is achieved.