Secure 3D CMOS Chip Stacks with Backside Buried Metal Power Delivery Networks for Distributed Decoupling Capacitance

Secure three-dimensional (3D) CMOS chip stacks with backside buried metal (BBM) routing provide low series impedance and high decoupling capability in a power delivery network (PDN), thanks to its distributed capacitances over a full-chip backside area. The Si demonstrator with cryptographic functionality was fabricated in a 0.13-μm CMOS technology with post-Si wafer-level BBM Cu processing with 10 μm, 15 μm and 35 μm of thickness, line width and space, along with through Si vias (TSVs) with 10 μm and 40 μm of diameter and depth, respectively. The capacitance of 0.18 nF/mm
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in the effective backside area of 71 mm
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suppressed dynamic IR drops in 10% and 59% for the single chip and four chip stack samples, respectively, during the operation of a 3.9M-gate crypto core at 30 MHz. This was confirmed by on-chip power noise monitoring. The 3D BBM PDN also effectively reduces power side channel information leakage, which is evaluated by 8x increase in the number of externally observed electromagnetic (EM) noise waveforms to attain the t-test value of larger than 4.5 if we assume the statistically effective correlation between EM noise emission and secret information in the crypto core.