Plasmonics: breaking the barriers of silicon photonics for high-performance chip-to-chip interconnects

High-performance computing systems are increasingly restricted by the bandwidth density and energy cost of electrical interconnection. While Si photonics can enable Tb/s chip-level bandwidth, challenges such as large device footprint, acute thermal sensitivity, and costly modifications to the CMOS front-end-of-line processes remain unresolved. This paper presents a plasmonic technology that breaks the barriers of Si photonics. Experimental demonstrations of monolithic, amorphous-based devices show more than 10× improvement in device footprint, the ability to withstand temperature fluctuation up to 100°C, and compatibility with backend integration. System-level simulations indicate up to 67× gain in bandwidth density and latency as well as 3.5× reduction in energy-per-bit for chip-to-chip interconnection. This paves the way towards novel, low-cost system-in-package interconnects and architectures using plasmonics.