Reliability and Performance of CMOS-Compatible Multi-Level Graphene Interconnects Incorporating Vias

Doped-multilayer-graphene (DMLG) interconnects employing the subtractive-etching (SE) process have opened a new pathway for designing interconnects for extremely scaled dimensions [1],[2]. Even though single-level scaled graphene wires have been demonstrated with comparable or lower resistivity and higher reliability w.r.t dual-damascene (DD) and SE-enabled metal-wires [1]-[3], the reliability and performance of a multi-level graphene interconnect technology (with vias) have remained elusive, which is of paramount importance for its integration in future technology nodes. This work, for the first time, addresses that need by engineering a CMOS-compatible solid-phase growth technique to yield large-area multilayer graphene (MLG) on both dielectric (SiO
₂
) and metallic (Cu) substrates, and subsequently demonstrating SE-enabled multilevel MLG-interconnects with edge-contacting metal-vias. Electrical and reliability characterizations establish that <; 2 % change in via resistance occurs under accelerated stress conditions, demonstrating supreme reliability of the multi-level MLG structure against self-heating and electromigration, as well as ~2-folds improvement in the estimated circuit performance of DMLG, making them ideal candidates for sub-10 nm nodes.