High hole mobilities in fully-strained Si/sub 1-x/Ge/sub x/ layers (0.3

Materials studies, hole transport measurements, and process and device simulations have been employed to determine the optimum epitaxial architecture of a fully-pseudomorphic Si/SiGe pMOSFET heterostructure that is intended for application in a near-standard CMOS process. Numerical simulations have shown that SiGe inter-diffusion severely limits the Ge content that can be achieved in a practical process flow. The SiGe hole wave-functions have been calculated and it is shown that hole confinement effects become very significant for SiGe layers less than 5 nm thick. Furthermore, estimates of the barrier penetration by the hole wave-function indicate that the beneficial effects of the buried-channel structure upon the hole mobility would be significantly reduced for Si cap thickness less than 2 nm. Buried-channel SiGe pMOSFETs are known to suffer from parallel conduction in the Si capping layer and calculations of the charge distribution indicate that high Ge contents (>30%) and thin Si cap thickness (<3 nm) are required in order to confine all of the inversion charge to the SiGe layer. The hole drift mobility has been measured at room temperature for fully-strained Si/sub 1-x/Ge/sub x/ layers with a range of alloy contents (0.3