A Multipole Approach Toward On-Chip Metal Routing for Reduced EM Side-Channel Leakage

With the proliferation of smart interconnected devices, the importance of securing computational data has increased manifold. While computational security layers like cryptographic algorithms protect against software-domain vulnerabilities, they cannot prevent leakage of electromagnetic (EM) fields from its parent device, hence compromising physical layer security. Most proposed methods of reducing EM side-channel leakage involve incorporating complex blocks into the design of an integrated circuit (IC). In this letter, we take an entirely novel stance, by borrowing fundamental concepts from multipole EM field decay and adapting the same for ICs by proposing a multipole routing approach. By building proof-of-concept scaled-up routing in PCBs, we demonstrate that unlike conventional dipole-style routing, metal layers incorporating higher-order multipoles result in a much faster-decaying side-channel leakage. Through detailed measurements, we infer guidelines toward optimizing the order of multipole needed to minimize side-channel leakage, thus enabling convenient implementation of physical layer security.