Localizing Hot-Carrier Degradation in Silicon Trench MOSFETs

Hot-carrier degradation (HCD) is investigated in silicon trench MOSFETs with field plate compensation. With the aid of charge pumping (CP), it is possible to obtain the total trap densities created by the hot-carrier stress. We will demonstrate that, in combination with TCAD simulations, profiling of the spatial distribution of the damage at the interface is possible in the accessible regions by extending the well-known reverse-bias CP method for planar devices to trench devices. Four process variations are investigated to show the impact of the cell geometry on the degradation location with the results being confirmed by capacitance measurements. It is found that the impact ionization rate seen in drift-diffusion TCAD simulations provides a straightforward means to estimate the defect locations.