F5: Enabling New System Architectures with 2.5D, 3D, and Chiplets

Summary form only given, as follows. The end of transistor scaling drives innovative 2.5D, 3D and chiplet technologies to further extend Moore’s law. Recent advancements in multi-die integration effectively reduce the costs at advanced nodes while providing more flexibility, modularity and heterogeneous integration, which require designers to rethink the system architectures to exploit these advantages. This forum focuses on the most recent advancements of the 2.5D, 3D and chiplet technologies as well as the key components for integration to enable new system architectures. This forum aims to bring together technologists, designers and architects from industry and academia to discuss the practical challenges and solutions in 2.5D/3D technologies, and to provide insights on how to leverage the technology benefits with different system requirements. The forum starts with an overview of foundry solutions on 2.5D, 3D and chiplets technologies, followed by deep dive topics inspired by application focuses. For example, FPGA with 2.5D/3D heterogeneous integration has emerged with promising data-centric applications. High-bandwidth memory (HBM) has been widely adopted in commercial processors, and yet advanced integration techniques and design strategies remain the key to overcome the practical challenges to satisfy power density and performance requirements. Recent advancements in chiplets rapidly evolves the design space in SoC, driving both cost reduction and modularity. Meanwhile, design considerations to address power delivery, signaling, and thermal challenges at the circuit level as well as advanced heterogeneous integration at the process level have attracted research interests and innovations to further improve the system-level efficiency and reliability in the multi-chip stacking era. Co-optimization of high-speed serial links with 2.5D/3D technologies plays another essential role to continuously improve off-chip communication and system performance. Moreover, driven by the growth of edge computing and advanced 3D stacking empowers sensor integration for latency reduction with near-sensor intelligence. Finally, the forum concludes with a hierarchical view of the 3D interconnect technology landscape and long-term roadmap, shedding light on future technology directions.