New embedded resistance/ gated diode on thin film silicon BIMOS device for advanced ESD protection in FD-SOI technology

The electrostatic discharge (ESD) protection is one of the main challenges for fully depleted silicon on insulator (FD-SOI) CMOS technologies. Several valuable solutions are already today using a BigMOS central clamp or a local protection. In the attempt to find an optimized solution, it is interesting to evaluate a BIMOS protection in thin silicon film according to a new design solution and new associated integration. In this paper, 28nm FD-SOI standard topology thin silicon film Bipolar MOS (BIMOS) devices with its external bias resistance and reverse diode is proposed. Moreover, the initial design has been modified by including the resistance and diode as embedded elements inside the BIMOS transistor leading to a novel design and topology solution. The solution aims at reducing the silicon area but also to keep the targeted ESD and DC performances. In addition, silicon demonstrators have been fabricated, characterized and discussed. It appears that the new solution is not only functional but it can be tuned according to the ESD technology window. Finally, this proposed solution can easily be transferred to another technology node just by changing the size of parameters.