Optimizing multiple EDA tools within the ASIC design flow

Selecting a single register transfer level (RTL) coding style-one that maximizes the performance of simulation, Boolean equivalence, and model checking while achieving an optimal flow through synthesis and physical design-is a formidable task. To reconcile competing tool-coding requirements, the Hewlett-Packard Richardson VLSI Lab has developed a coding style and a design flow methodology that incorporates modern programming language principles. Using the principles of information hiding, abstraction, and encapsulation on all functional grouping of state elements (and other objects), our engineers can focus on design functionality rather than on each individual electronic design automation (EDA) tool's optimal coding style requirement. Building on these principles, we have developed a design methodology to automate the generation of tool-specific libraries. This methodology, which optimizes multiple process points within the application-specific integrated circuit (ASIC) design flow, has several advantages: It permits a seamless optimization of design processes throughout the course of design and enables augmentation of new processes. It leaves the designer's text and functional intent undisturbed throughout the design's duration. It offers cooperation and support for multiple EDA tools while achieving higher verification coverage in minimal time. Finally, our approach clarifies the design intent at the RTL, increases design productivity, and raises the abstraction level without forcing the designer to adopt a new hardware description language (I-IDL).