TCAD model calibration for the SiC/SiO2 interface trap distribution of a planar SiC MOSFET

Silicon carbide (SiC) metal-oxide-semiconductor field effect transistor (MOSFETs) are gradually replacing silicon power devices in many applications because of the higher performances of the material. Even if the technology for SiC MOSFET has been improved in the last years, the very high interface SiO2/SiC trap density is still a problem that affects the present SiC MOSFET generations. This issue is still not addressed in technology computer aided design (TCAD) simulations supporting the devices development. In this work we demonstrate how an accurate calibration of the TCAD model of a commercial SiC MOSFET is only possible by considering a non-uniform trap distribution along the SiO₂ SiC interface.