A 2GS/s 14-bit 25dBm OIP3 Current-Steering DAC in 45nm CMOS Technology

In this paper, a 2GSps 14-bit current-steering digital-to-analog converter is presented. Quad-switch is used to achieve 2X sample rate with two lanes of input data. A clock duty calibration block is added to improve quad-switching performance. Other techniques such as dynamic element match, cascode always on are adopted to counter the non-linearity of the circuits. The design has been fabricated in TSMC 45nm 1P10M CMOS technology. Two tone test results show an above 25dBm output third order intermodulation intercept point ranged from 100MHz to 900MHz. The design occupies an area of 0.7mm
²
and has a power dissipation of 276mW.