Minimal Aliasing Single-Error-Correction Codes for DRAM Reliability Improvement

We discuss the problem of finding a minimal aliasing code among a class of systematic single-error-correction codes that are suitable to be implemented within DRAM die, as opposed to external ECC used in memory controller outside of DRAM chip. We prove a sharp lower bound of aliasing probability and propose a simple method to come up with a code that meets the bound. By an experiment, we also demonstrate that a randomly chosen code is likely to have much more aliasings with overwhelmingly high probability.