2.3 kV 4H-SiC Planar-Gate Accumulation Channel Power JBSFETs: Analysis of Experimental Data

Experimental results obtained for 2.3 kV SiC planar-gate power JBSFETs with different cell topologies are analyzed in this article using analytical models and numerical simulations. All the accumulation-channel devices were simultaneously manufactured in a 6-inch commercial foundry with channel length of 0.5 μm and gate oxide thickness of 55 nm. The Schottky contact width was chosen to achieve an on-state voltage drop of below 2.8 V in the 3
^rd
quadrant for the integrated JBS diodes. Lower specific on-resistance of the Hexagonal and higher values for the Octagonal cell topologies compared with the conventional Linear cell design were experimentally observed. New analytical models developed for the various cell topologies reveal that these differences arise from changes in the relative contributions from the N
⁺
source contact, channel, and accumulation region resistances. The analysis reported in this article provides new insight on the importance of the accumulation layer resistance to the Octagonal cell topology. Numerical simulation reveal that the measured leakage current behavior correlates with the electric field observed at the Schottky contact within the 2.3 kV JBSFET cell structures. The leakage current begins to rise rapidly when the electric field exceeds 1.5 MV/cm due to Schottky barrier lowering and enhanced tunneling. The reverse transfer capacitance and gate charge were found to correlate with the JFET region density within the different cell topologies. The measured on-state voltage drop in the third quadrant was found to correlate with the JBS diode density in the cell topologies. A new high-frequency figure-of-merit [V
_f3Q
*
Q
_gd,sp
] is proposed for SiC JBSFETs. The Octagonal cell designs are found to be the most suitable for high frequency applications of 2.3 kV JBSFETs based on the HF-FOMs [R
_on
*
Q
_gd
] and [V
_f3Q
*
Q
_gd,sp
].