A Scalable Software Defined Network Orchestrator for Photonic Network on Chips

Photonic networks and software-defined networks are two promising technologies to improve network-on-chips performance, scalability, and resource utilization. Several architectures suffer from scaling limitations, high-power consumption, and noise interference drawbacks. In this paper, an enhanced photonic network-on-chip architecture called (SD-PNoC) is presented. The proposed architecture based on a hybrid hardware-software approach, and a Software-Defined Management Orchestrator (SDMO) to separate the network control and data forwarding planes. This orchestrator has hosted on the upper hardware router as a virtual layer capable of dynamic management. It reconfigures data forwarding paths and allows dynamic execution of different algorithms in real-time, as it scales the proposed topology based on both applications and the network requirements. The proposed SD-PNoC architecture, hierarchical communication protocols, and orchestrator management policies were implemented, simulated, and tested using a customized Phoenix-SIM framework in the OMNIT++ simulation environment. Numerous simulation experiments under different conditions have been performed and have proven that the performance of the proposed architecture is better than that of the conventional electronic network on chip (ENoC). Furthermore, simulation results without using the management policies showed that the latency is reduced by 46% and 25.5% for the
$4\times 4$
and
$8\times 8$
network structures, respectively. While the power consumption is reduced by 76.5% and 78.5% for the
$4\times 4$
and
$8\times 8$
network structures, respectively. Besides, the chip area is reduced by 33.4%. Moreover, simulation results of SDMO with using the management policies for the
$8\times 8$
network structures increased the enhancement of latency from 25.5% to 37.3% and the power consumption from 78.5% to approximately 80%, which assure the ability of the proposed architecture to remarkably enhance the overall performance of complex network-on-chip structures.