A 0.115 /spl mu/m/sup 2/ 8F/sup 2/ DRAM working cell with LPRD (low parasitic resistance device) and poly metal gate technology for gigabit DRAM

An 8F/sup 2/ stack DRAM cell, 0.115 /spl mu/m/sup 2/ in size, has been successfully integrated using a selective epitaxial plug scheme for landing plug contacts and poly metal gates and MIM COB capacitors, by which cell working has been proven under easy function check mode. The cell transistor exhibits sufficient saturation current (I/sub OP/) of >40 /spl mu/A with threshold voltage (V/sub tsat/) of 1.0 V.