Simulation-Based Power-Loss Optimization of General-Purpose High-Voltage SiC MOSFET Circuit Under High-Frequency Operation

This investigation focuses on a simulation-based power-loss optimization scheme, which is applied to laboratory developed general-purpose inverter-stack circuit, fabricated using high-voltage SiC-MOSFET. The optimization mainly addresses the external elements under fixed output current. It is found, that an increase in switching frequency causes increased loss, which is however less than that calculated by following the conventionally predicted linear dependence on the frequency. The switching loss is also strongly varying, in accordance with the output current variation, which is determined by the circuit requirements. Here, it is demonstrated, that circuit simulation with an accurate compact model can be successfully applied to realize significant improvements, leading to lower power loss under the requested operating condition. It is also found that the SiC-MOSFET can maintain the efficiency of nearly 98% even for high-frequency operations.