Source/Drain Extension Doping Engineering for Variability Suppression and Performance Enhancement in 3-nm Node FinFETs

In this article, variability suppression and performance enhancement through source/drain extension (SDE) module engineering is demonstrated in 3-nm node fin field-effect transistors (FinFETs). The process variabilities induced by different modules are systematically quantified in 3-nm node FinFETs using fully calibrated technology computer-aided design (TCAD) tools. With experimentally characterized geometry parameters and their variation ranges, the fin and the SDE module are identified as the main variability sources. The unique device performances induced by the realistic fin and SDE modules are interpreted. Previously developed for performance enhancement in 7- and 10-nm node FinFETs, 3-D SDE doping profile engineering can effectively reduce fin and SDE module-induced variabilities by
$4.0\times $
(
$2.7\times $
) and
$1.8\times $
(
$2.1\times $
) in 3-nm node n-(p-)FinFETs, respectively. In addition, the precise control of the vertical SDE profile enables a new dimension for design optimization. An optimization methodology for the 3-D SDE doping profile is demonstrated, achieving a 7% (10%) ON-state current enhancement in 3-nm node n-(p-)FinFETs.