A High-Speed Low-Power Flash ADC with Continued Pipelined Gating in 28-nm CMOS

A flash analog-to-digital converter (ADC) with 6-bit and 10 GS/s is proposed for 28-nm CMOS process. The proposed continued pipelined clock triggers the dynamic amplifier and two-stage comparator to improve the conversion speed of the ADC. Moreover, a non-binary flash conversion architecture is designed, which utilizes the edge comparators to increase the effective number of bits. The bubble and meta-stability issues are both addressed by logic gates. The measured SNDR and SFDR were 37.53 dB and 43.22 dB, respectively, with a 0.46-GHz input at 10 GS/s operation while consuming 32.6 mW of total power. At 10 GS/s, the ADC consumes 32.6 mW from a 1.0-V supply voltage in 28-nm CMOS process and achieves a Schreier figure of merit of 146 dB.