Efficient Hardware Realization of a New Variable Regularized PAST Algorithm With Multiple Deflation

This paper proposes a new variant of the projection approximation subspace tracking (PAST) algorithm with multiple deflation (MD) and its efficient hardware architecture. It extends the PAST with deflation (PAST-d) algorithm by performing multiple deflations at each step and relies on a recently introduced variable forgetting factor, and variable regularized PAST algorithm to improve the overall convergence rate, steady-state error, and numerical properties. It shares the same simple hardware structure of the PAST-d algorithm in pipeline realization but offering a more flexible tradeoff between complexity and performance. Moreover, methods for estimating the eigenvalues and the dimension of the signal subspace are proposed. Novel simplifications of the proposed variable forgetting factor (VFF) and variable regularization (VR) PAST-MD algorithm are also developed to avoid the expensive cubic root and division operations involved to facilitate its hardware implementation. Moreover, a combined data-regularization update is introduced to avoid the additional QR decomposition (QRD) update associated with the regularization, at the expense of very slight performance degradation. A novel pipelined hardware implementation of the simplified VFF-VR-PAST-MD algorithm based on the QRD and the COordinate Rotation DIgital Computer (CORDIC) is also proposed and implemented in Xilinx field programmable gate array (FPGA). Thanks to the proposed “root- and division- free” schemes, our proposed architecture can achieve around 20.2% higher working speed and save 1.9% lookup tables (LUTs), 1.8% slice register, and 22.8% digital signal processors (DSPs) over conventional implementation of the proposed architecture. Compared to the previous work, which is based on PAST-d algorithm, the proposed QRD-based algorithms offer better performance and a more flexible tradeoff between hardware resources and performance.