AXI Based Three 8-bit Parallel Input to One Serial Output Converter with Priority Management System and Asynchronous Clocks at Input and Output

As the technology advances, more systems are integrated on a System on chip (SoC), hence more units require interconnection. Different systems operate at different clocks. Since, in traditionally used bus architecture, transmitter and receiver use the same clock, using independent clocks at transmitter and receiver will results in Clock Domain Crossing issues. Also, considering advantages of serial communication over parallel , parallel to serial converters are essential digital element.Considering these requirements, a parallel to serial converter with input and output at asynchronous clock is an essential element of future Soc. To address this need, we propose an 8-bit parallel to serial converter with asynchronous FIFO, connecting multiple masters and slaves. This system has Arbitration controlled Priority management. Based on the arbitration policy selected, one of the Masters will pass data serially to slave. By resource sharing, we saved 13% of sub-system power and 20 flip-flops and 38 Look-up-tables( LUTs).