Frequency Multiplier using Phase-Locked Loop

A Phase-Locked Loop (PLL) Frequency multiplier application is been presented in this paper. The designed PLL is a type-2, order-3 CPPLL with a tuning range of 143-176M Hz with the center frequency of 160M Hz and a loop bandwidth of 2M Hz. The functional blocks of the PLL Frequency multiplier include PFD, Charge Pump with a loop filter, a voltage-controlled oscillator with constant gain(Kvco) over entire operating range and a frequency divider. All the blocks are optimized across PVT variations. The voltage-controlled oscillator (VCO) is designed using various optimization techniques for its better performance, the Charge Pump design is a "Gate driven" and the frequency divider works on Clocked CMOS logic whose advantages and implementations will be discussed further in the paper.