A 66-400 MHz, adaptive-lock-mode DLL circuit with duty-cycle error correction [for SDRAMs]

A DLL circuit featuring variable "lock mode" and correction of duty-cycle error is described. The DLL circuit has a wide locking range from under 66 MHz to 400 MHz. The chip area and power consumption at 400 MHz are 0.33 mm/sup 2/ and 24 mW, respectively.